Certain programmable logic devices use programmable look-up tables to perform logic functions. The outputs of such look-up tables can be combined together using similar look-up tables to provide more complex functions.
Look-up tables which are used for performing elementary logic functions can also be used for performing some “special” functions like addition, subtraction, counting, etc. However, to perform such functions, the size of a look-up table will typically need to be quite large. To perform one-bit full addition, two look-up tables are used, one for computing the sum and one for generating the carry. For example, four input look-up tables may be an apropriate size for general use, but they may be larger than necessary for one-bit full adders or counters. Thus, it is a waste of resources to use such a look-up table for addition or counting.
Nonetheless, counters and adders are commonly used in digital logic. If addition or counting of larger numbers of bits is required, then more look-up tables are also required (two for each bit of operation). This results in reduced speed of operation and increased waste of look-up table resources.
U.S. Pat. Nos. 5,481,486 and 5,274,581, both to to Cliff et al., describe look-up tables for use in programmable logic devices which are modified to be used as adders, substractors, and various types of counters. The invention in these patents divide four input look-up tables (LUTs) into two, three-input LUTs for implementing the arthimetic functions. Yet, these tables implement only one-bit full addition because they are using the first three-input LUT for sum generation bits and the other three-input LUTs to generate the bits to control the carry logic. Thus, a four-input LUT with a single output and a carry logic is provided.